Acrosser offers various standard form factor embedded single board computer(SBC) ranges from PC/104, PCI-104, 3.5”SBC, EPIC to Mini ITX. They feature with fanless, low power, industrial grade design, rich I/O, compact and low profile. Acrosser also provide the service of custom design to meet your special requirement such as extended temperature and medical applications.
In Fall 2021, Acrosser Technology is introducing its 3 new network appliance products, including AND-El6KE1, AND-APL1E1/E2, and ANR-C246E1, to all customers.
The AND-EL6KE1 is equipped with the latest Intel® Celeron® J6000 /Pentium® N6000 series/Atom™ x6000E series processors (formerly Elkhart Lake). This new product is specially designed to satisfy every aspect of UTM, NGFW, firewall, VPN, SDN, NFV, vCPE, and SD-WAN service providers.
To enhance the product reliability, AND-EL6KE1 built a redundant power supply to prevent unpredictable accidents. To empower the connection ability, AND-EL6KE1 is equipped with 4 copper Gigabit RJ-45 LAN ports and 1 fiber SFP port, and also provides 6 antenna ports and 3 Mini PCIe slots (co-lay with M.2) to increase wireless flexibility. Up to three wireless modules can be installed at the same time in AND-EL6KE1 (including multiple Wi-Fi and Bluetooth networks and 4G and 5G cellular modules).
Overall speaking, AND-EL6KE1 is perfect for UTM, NGFW, firewall, VPN, SDN, NFV, vCPE, and SD-WAN.
The AND-APL1E1/E2 is a new ultra-compact network box with a 155 x 92 x 32 mm tiny size dimension. It is powered by Intel® N3350 SoC and designed to be easy to deploy in home offices, small businesses, and branch offices as well.
Even AND-APL1E1/E2 is such a small network box, Acorsser still designs it as a durable, reliable network appliance. It is definitely a good choice for budget buyers and ideal for deployment as a VPN, Firewall, SD-WAN, NAC, vCPE in any environment with a limited budget.
The Major Specifications of Acrosser AND-APL1E1/E2
The ANR-C246E1rackmountnetwork appliance is equipped with a power Intel® 8/9th Gen and Xeon E, Core™ i7/i5/i3 processors in smaller rackmount chassis of 430(W) x 44(H) x 200(D)mm dimension. This design can provide customers a more flexible choice in rackmount servers.
The ANR-C246E1 provides a more flexible server platform & system expansion versatility with 8x GbE copper LANs, 1 x expandable network interface modules (Exp. NIM), 1 Console, 2x USB 3.2 Gen 1, 2 x SO-DIMM DDR4, 2 x 2.5"SATA-III, and 1 x mPCIe/mSATA socket. The ANR-C246E1 is also equipped with an LCM display with 4-key buttons. Withing these powerful computing abilities and outstanding network communication abilities, ANR-C246E1 is perfect to apply to UTM, vCPE of SDN/NFV structure, fog node of cloud computing, and IoT gateway.
The Major Specifications of Acrosser ANR-C246E1
Intel® 8/9th Gen Xeon E, Core™ i7/i5/i3
2 x SO-DIMM DDR4
1 x Exp. NIM (1G/10G/40G, Fiber/Copper/LAN Bypass)
8 x GbE Copper with 2-pairs LAN Bypass
2 x 2.5" or 1x 3.5” SATA-III
1 x mPCIe/mSATA socket
Acrosser is 100% committed to providing its OEM/ ODM/ JDM and end-user clientele with high-quality innovative networking appliances and embedded computer solutions for shorter time-to-market and in achieving higher competence to win business opportunities in the marketplace. For more information, please visit: https://www.acrosser.com/en/Contact/Inquiry
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In order to provide customer more choices in entry-level network solution, today ACROSSER Technology, a world-leading network appliance supplier, proudly revealed its latest micro box fan-less network appliance -AND-APL1N1FL series.
The fan-less micro box network appliance, AND-APL1N1FL, can offer the utmost connectivity with a compact form factor at dimensions 280 x 209 x 44 mm (11.02” x 8.23” x 1.73”). In addition, AND-APL1N1FL also supports 3-pair LAN bypass for Ethernet connection and provides a luxurious set of I/O, including one mini PCIe slot to support WiFi or 4G, three USB3.0 ports on the rear panel, one console port (RJ45), 8-bit GPIO on board pin header, and one SATA III port or mSATA socket. Rich I/O ports and drive bays are designed for easy access and maintenance.
AND-APL1N1FL, with compact size and reasonable cost, is the perfect solution for small office network solution, UTM, mail server and firewall applications. AND-APL1N1FL Specifications:
1. Intel® Apollo Lake SoC J-series/N-series/E-series
2. 1 x SO-DIMM DDR3L-1866 MHz, up to 8GB
3. 6 x GbE, 3 x USB
4. 1 x Mini PCIe Socket
5. 8 x GPIO
This new Apollo Lake network appliance: AND-APL1N1FL is designed with customers looking for a cost-effective niche solution in mind. Samples are available upon request; please contact us via online inquiry system: http://www.acrosser.com/inquiry.html
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Today, Acrosser Technology announces a spring sale to all customers. In this special promotion, Acrosser offers a cost-effective 3.5” embedded CPU board, AMB-BT19S1, at US$175 only for MOQ 100pcs.
AMB-BT19S1, an embedded CPU board at 3.5” form factor, is compact but come with rich I/O ports for high flexibility and easy expansion capabilities. Built-in Intel low power Bay Trail CPU, it could run in applications that demand reliable operation, consistent performance, and high quality in a harsh industrial environment. In other words, it is suitable for all sorts of industries like factory automation, medical instrument, digital signage, Kiosk, public information station, ATM, M to M, IoT Application and entertainment equipment.
For the very first time, Acrosser offers all customers a real bargain at the very low price, however, the VIP service as well. You get to enjoy the low price, performance, quality and VIP service all at the same time. It’s time to jump on the bandwagon and take the advantage!!!
Customers from the US, Canada or Latin America, please call our toll free number +1-886-401-6463 or send your inquiry through our online inquiry system: http://www.acrosser.com/inquiry.html
Features ● Intel Bay Trail SoC, low power consumption. ● 3.5” form factor ● 1 x DDR3L-1333MHz, SO-DIMM, up to 8GB ● 8 x USB port (2 x USB 3.0, 6 x USB 2.0), 6 x COM ● 2 x GbE LAN, 2 x mini PCIe, 1 x SIM slot ● 1 x SATA II, 1 x mSATA ● Dual Display port -VGA & LVDS ● 12V Input ● Fanless design
Acrosser is a leading global industrial computer manufacturer, which released the AIV-QM97V1FL fan-less series In-vehicle computer. It is based on Intel’s fifth generation Broadwell CPU that has great power efficiency ratio (super low power consumption & high performance) performance and uses a fan-less ultra-thin body design with reduced heatsink volume to lower the overall weight of the product. In addition, this computer can be equipped with M.2 2280 SSD, forming two storage areas with the 2.5-inch SSD to ensure high-speed access and super large capacity. It can also be equipped with the Sierra 4G LTE & GPS module, Wi-Fi & BT modules. The SIM card also uses a removable design to satisfy different needs by customers. Another thing worth mentioning is that the smart In-vehicle power management of this product can even allow customers to adjust the BIOS according to their own needs for control. With the rise of Industry 4.0, In-vehicle computers have more diverse applications and excellent solutions for industries. Acrosser has professional wireless computing, GPS systems, power management, In-vehicle touch control systems and other related technologies that can be widely applied on public transportation, for example, screen solutions that can be used independently as kiosk, whether for touch control navigation or multimedia playback integrated systems, or for advertisement message services in buses and trams. The fan-less design makes industrial tablets great solutions. Passengers can enjoy the content on the screen without the interference of noise. You are welcomed to contact Acrosser’s sales team to acquire product and price related information. Contact Us: http://www.acrosser.com/inquiry.html Subscribe to our social media sites and stay connected! industrial pc, industrial computer, Rackmount server, Embedded single board computer, in cab computer,
As shown in the picture, additional security elements include multiple solutions. TenAsys also offers the INtime RTOS family, which can run as a stand-alone RTOS or alongside Microsoft Windows as shown. Both products enable users to partition a multicore platform to run mixed fanless embedded systems, making better use of the processor’s advanced features to provide highly integrated solutions. (Microsoft and TenAsys are both Associate members of the Alliance.)A factory is only as strong as its weakest link, so every Internet of Things client in the factory needs protection from viruses, malware, and hacking to prevent costly interruptions to factory operation. The 4th generation Intel Core processor adds a number of features to its security portfolio, including McAfee’s Deep Defender technology, which resides between the memory and embedded system to perform real-time memory and CPU monitoring without impacting overall system performance.
They work in harsh environments, and they get little or no recognition. But their impact on power plant efficiency can be significant. Valves and actuators are critical in almost every aspect of single board computer.
"There will be a lot of knowledge at this event," said Richard Blackburn, Event Organiser. "This will be a chance for engineers to get up to date and explore new technologies and trends in the industry. Whether it's hardware, software, enclosure or test, I think they will find this a very useful event." Distributor of embedded systems tools and technologies embedded computer. Systems will be exhibiting its Timesys embedded Linux OS solution and also giving a presentation on the management of open source software for commercial projects. "We are very pleased to be supporting this new event," said Stuart Parker, Managing Director of SDC Systems. "The UK is very successful in the field of electronics and embedded computing and has needed such a conference for quite a embedded computer while now. refer to: http://embedded-computing.com/news/embedded-oss-the-device-developers-conference/
2013 the Embedded Systems Expo and Conference (ESEC) from May 8th to the 10th. The event will take place at the Tokyo International Exhibition Center in Tokyo, Japan. We warmly invite all customers to come and meet us at the west hall, booth number: WEST 10-61.
Given the increased complexity of processors and applications, the current generation of Operating Systems (OSs) focuses mostly on software integrity while partially neglecting the need to extract maximum performance out of the existing hardware.
Processors perform as well as OSs allow them to. A computing platform, embedded or otherwise, consists of not only physical resources – memory, CPU cores, peripherals, and buses – managed with some success by resource partitioning (virtualization), but also performance resources such as CPU cycles, clock speed, memory and I/O bandwidth, and main/cache memory space. These resources are managed by ancient methods like priority or time slices or not managed at all. As a result, processors are underutilized and consume too much energy, robbing them of their true performance potential.
Most existing management schemes are fragmented. CPU cycles are managed by priorities and temporal isolation, meaning applications that need to finish in a preset amount of time are reserved that time, whether they actually need it or not. Because execution time is not safely predictable due to cache misses, miss speculation, and I/O blocking, the reserved time is typically longer than it needs to be. To ensure that the modem stack in a smartphone receives enough CPU cycles to carry on a call, other applications might be restricted to not run concurrently. This explains why some users of an unnamed brand handset complain that when the phone rings, GPS drops.
Separate from this, power management has recently received a great deal of interest. Notice the “separate” characterization. Most deployed solutions are good at detecting idle times, use modes with slow system response, or particular applications where the CPU can run at lower clock speeds and thus save energy. For example, Intel came up with Hurry Up and Get Idle (HUGI). To understand HUGI, consider this analogy: Someone can use an Indy car at full speed to reach a destination and then park it, but perhaps using a Prius to get there just in time would be more practical. Which do you think uses less gas? Power management based on use modes has too coarse a granularity to effectively mine all energy reduction opportunities all the time.
refer: http://embedded-computing.com/articles/performance-management-new-dimension-operating-systems/
Understanding and selecting analog IP can be risky, but engineers today have more choices and more control than they think. Knowing how to manage the IP selection process can help engineers effectively meet objectives and reduce risk.
Analog IP landscape
The analog IP market has exploded in the past 10 years. Demand for ADC, DAC, Phase-Locked Loop (PLL), and DC-DC converter IP is expected to grow at more than 17 percent through 2015, according to Semico. Two forces are largely responsible for this. First, the amount of analog talent in the labor pool has reduced dramatically. Second, competitive pressures are putting premiums on time to market and costs. IP is seen as an effective strategy for meeting time to market and addressing significant bottleneck issues because it allows engineers to purchase blocks and amortize the cost over multiple projects.
Strategy + business model
Analog IP firms invest heavily in R&D to lead on the performance front and then market those products for a variety of applications. The model works great for innovation and for customers needing state-of-the-art performance. Performance premiums are often not necessary for the application. This is where proper requirements definition comes in handy.
Most analog IP firms charge upfront license, per-unit royalty, and related maintenance and service fees. Licenses can usually be expanded from single use to multisite to amortize costs more efficiently (see Figure 1).
Figure 1: An analog IP business model allows engineers to purchase blocks and amortize the cost over multiple projects.
Analog IP challenges
Because analog IP blocks are usually delivered as hard macros, they are largely dependent on process technology and are difficult to modify and test. This decreases the number of options and can make a customer more reliant on a specific foundry. Analog IP companies are exerting a great deal of effort to migrate their portfolios to smaller technologies, but are seeing major challenges at 40 nm and below. This has long-term implications for product roadmaps as costs grow exponentially at smaller technologies. These challenges present strategic trade-offs for embedded teams.
When ADC, DAC, or DC-DC controller IP is developed in all-digital RTL, many of these challenges are removed. All-digital ADC cores, for instance, are easily modified for special requirements, technology independent, FPGA embeddable, and digitally testable. These cores are often smaller and lower power due to the use of a digital fabric. The drawback of this approach is limited resolution and bandwidth. At Stellamar, ADCs currently offer up to 16-bit resolution and 400 kHz bandwidth. By comparison, analog ADCs offered in mixed-signal FPGA packages provide 12 bits and 500 kHz bandwidth.
Steps to evaluate IP/system fit
With a high-level understanding of the analog IP landscape, engineers can concentrate on avoiding the two most common problems when selecting IP: unclear objectives and improper requirements definition. To do this, a team considering buying IP must thoroughly understand these two dynamics.
Project objectives
Given the trade-off of offering smaller technologies at higher costs, clarity on the most important overall project objectives is critical. Analog IP is one tool of many that can help engineers meet an objective, and whatever tool is chosen dictates how the team allocates resources to meet the objective.
One of the best tools for prioritizing objectives is the CARVER matrix that Navy SEALs use to assess the value of a military target in a quick, no-fail way. This exercise can shed light on the most important issues to the design team, including reuse versus custom, foundry reliance, and technology portability and prototyping. Try this exercise in a group or individually to compare how team members view objectives.
First, list critical objectives for the embedded design project. Be specific. Objectives such as low power and small area aren’t nearly as effective as actual numbers. Objectives should also include higher-level strategies such as “foundry neutral” or “ensures process roadmap.”
Next, score the objectives 1-5 (5 being highest) on each of six criteria:
Criticality: How critical is this objective?
Accessibility: How achievable is the objective with internal resources? Purchased IP?
Recognizability: Does the team recognize the objective as important?
Vulnerability: What force is needed to achieve the objective? Can it be achieved in a certain time frame? Are large amounts of resources needed?
Effect on mission: How much closer does this objective get the design to meeting the overall strategy?
Return on effort (ROI): How much bang for my buck?
Table 1 shows an example CARVER matrix.
Table 1: A CARVER analysis can shed light on an IP project by rating the importance of design objectives according to six critical factors.
In this example, the team’s overall strategic objectives are to limit reliance on one foundry and ensure the IP can get the product to 22 nm. These objectives are achievable in the current IP landscape if technical requirements can be met, leading to the next dynamic of understanding.
Technical requirements
In the old days of in-house IP development, engineers would gather requirements and build IP blocks exactly according to those specs. This often increased cost, lead times, and risk when targeting a new technology. As cost and time-to-market pressures have transferred IP production to the “outhouse,” adherence to specifications has relaxed. This benefits IP companies who market their higher-performance blocks for wide-ranging, lower-performance applications.
A vendor has limited ability to meet specific requirements in a given budget or time frame. Foundry and process portability challenges further limit optimal choices for the customer. These limits have ramifications from higher power consumption to price premiums for unnecessary performance. Proper requirements definition is key to understanding where trade-offs will occur and how those trade-offs can be counterbalanced.
To start proper requirements definition, some key questions need to be asked, including:
What is being measured, and what is needed?
What are the minimum resolution and bandwidth needed to completely convert the input?
What are the power and size budgets?
What are the input characteristics?
Are there unique timing needs?
Is the prototype system FPGA-based?
How can the design convert from FPGA to ASIC?
What foundry created the IP? What process was used?
What are the test requirements?
Standards exist for many functions. For instance, audio is still 12 bits and 15 kHz bandwidth. Professional audio is higher, and knowing this difference can save money and time. As another example, many DC-type measurements have very small bandwidth, often sub-10 Hz, yet engineers often choose ADC IP with greater than 1 MHz bandwidth because of availability. This is like using a sledgehammer to drive the head of a pin. It gets the job done, but will consume more power than necessary. Similarly, integral and differential nonlinearity degrades the effective number of bits for some ADCs. If the requirement is 12 bits, a 14-bit ADC block might be needed to achieve the required 12-bit resolution.
IP selection
Armed with prioritized strategic objectives and exact technical requirements, the team can start the selection process. Websites such as Chipestimate.com and Design-reuse.com are good places to start. Xilinx and Microsemi also provide robust IP ecosystems that include analog IP functions from providers like Stellamar.
To attain the level of comfort needed to make a selection, the team must ask the vendor a number of questions, including:
Does the vendor have customers and success stories?
Are the cores silicon-proven?
What level of support is provided?
Can the core be evaluated before purchase?
What deliverables are provided?
What is the licensing structure?
How long will it take to tailor IP to specific needs?
How long has the company been providing IP cores?
How free is the company with sharing basic information?
What strategic partnerships does the vendor have?
By following this roadmap in sequence and asking all of the important questions, the design team should be confident that third-party analog IP selection and integration can help meet strategic objectives and add significant value to the overall system design.
